gecko3:gecko3main:ucf_file [Gecko Development Platform]

############################################################ # # Gecko3 SoC HW/SW Development Board # _ _ _ _ # ( _`\ ( )( ) ( ) # | (_) )| ( | |_| | Bern University of Applied Sciences # | _ <'| _) | _ | School of Engineering and # | (_) )| | | | | | Information Technology # (__/'(_) (_) (_) # # # Author: Christoph Zimmermann # Date of creation: 22.08.2007 # Description: # constraint file for the first version of the GECKO3main # only onboard peripherie is located here # ############################################################

## System level constraints NET “sys_clk_pin” LOC = “af14” ; # on-board Clock oszillator, 50 MHz NET “sys_rst_pin” LOC = “ae19” ; # active low system reset. wired to button 4 (reset) and system bus

Net sys_clk_pin TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps; Net sys_rst_pin TIG;

Net fpga_0_Micron_DDR_1_CLK_FB_pin TNM_NET = fpga_0_Micron_DDR_1_CLK_FB_pin; TIMESPEC TS_fpga_0_Micron_DDR_1_CLK_FB_pin = PERIOD fpga_0_Micron_DDR_1_CLK_FB_pin 12000 ps;

#Switches and Buttons NET “fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<0>” LOC = “d6” ; #this is switch3 in the schematic! NET “fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<1>” LOC = “c6” ; NET “fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<2>” LOC = “f7” ; NET “fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<3>” LOC = “d7” ; #this is switch0 in the schematic! NET “fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<4>” LOC = “e12” ; #this is button2 in the schematic! NET “fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<5>” LOC = “g10” ; NET “fpga_0_Push_Buttons_and_Switches_GPIO_in_pin<6>” LOC = “e7” ; #this is button0 in the schematic!

#LEDs NET “fpga_0_LEDS_GPIO_d_out_pin<0>” LOC = “c13” | SLEW = SLOW ; #this is LED7 in the schematic! NET “fpga_0_LEDS_GPIO_d_out_pin<1>” LOC = “d13” | SLEW = SLOW ; NET “fpga_0_LEDS_GPIO_d_out_pin<2>” LOC = “e13” | SLEW = SLOW ; NET “fpga_0_LEDS_GPIO_d_out_pin<3>” LOC = “c12” | SLEW = SLOW ; NET “fpga_0_LEDS_GPIO_d_out_pin<4>” LOC = “e10” | SLEW = SLOW ; NET “fpga_0_LEDS_GPIO_d_out_pin<5>” LOC = “f10” | SLEW = SLOW ; NET “fpga_0_LEDS_GPIO_d_out_pin<6>” LOC = “g9” | SLEW = SLOW ; NET “fpga_0_LEDS_GPIO_d_out_pin<7>” LOC = “f9” | SLEW = SLOW ; #this is LED0 in the schematic!

#RS232 UART NET “fpga_0_RS232_RX_pin” LOC = “ac7” ; NET “fpga_0_RS232_TX_pin” LOC = “ac6” ;

#Ethernet PHY NET “fpga_0_Ethernet_10_100_PHY_col_pin” LOC = “af5” ; NET “fpga_0_Ethernet_10_100_PHY_crs_pin” LOC = “af7” ; NET “fpga_0_Ethernet_10_100_PHY_dv_pin” LOC = “ad5” ; NET “fpga_0_Ethernet_10_100_PHY_pwr_down_pin” LOC = “ad12” ; NET “fpga_0_Ethernet_10_100_PHY_rst_n_pin” LOC = “af13” ; NET “fpga_0_Ethernet_10_100_PHY_rx_clk_pin” LOC = “ae7” ; NET “fpga_0_Ethernet_10_100_PHY_rx_data_pin<0>” LOC = “ad6” ; NET “fpga_0_Ethernet_10_100_PHY_rx_data_pin<1>” LOC = “af8” ; NET “fpga_0_Ethernet_10_100_PHY_rx_data_pin<2>” LOC = “ae4” ; NET “fpga_0_Ethernet_10_100_PHY_rx_data_pin<3>” LOC = “ae8” ; NET “fpga_0_Ethernet_10_100_PHY_rx_er_pin” LOC = “ad4” ; NET “fpga_0_Ethernet_10_100_PHY_tx_clk_pin” LOC = “ab9” ; NET “fpga_0_Ethernet_10_100_PHY_tx_data_pin<0>” LOC = “ab11” ; NET “fpga_0_Ethernet_10_100_PHY_tx_data_pin<1>” LOC = “ac10” ; NET “fpga_0_Ethernet_10_100_PHY_tx_data_pin<2>” LOC = “ac11” ; NET “fpga_0_Ethernet_10_100_PHY_tx_data_pin<3>” LOC = “ad10” ; NET “fpga_0_Ethernet_10_100_PHY_tx_en_pin” LOC = “ab10” ;

#SPI bus, connectet to the M25P32 serial flash memory, contains FPGA *.bin files NET “fpga_0_Generic_SPI_CS_pin<0>” LOC = “y8” | SLEW = SLOW ; NET “fpga_0_Generic_SPI_MISO_pin” LOC = “aa11” | SLEW = SLOW ; NET “fpga_0_Generic_SPI_MOSI_pin” LOC = “aa9” | SLEW = SLOW ; NET “fpga_0_Generic_SPI_SCK_pin” LOC = “aa10” | SLEW = SLOW ;

# Flash memory interface, we use two Intel NOR flash chips with a 32 bit databus #here we change the bit order from big-endian (OPB like) #to little-endian # start address Bus NET “fpga_0_Intel_StrataFlash_Mem_A_pin<7>” LOC = “g16” ; #this pin is in the schematic Flash_A23! NET “fpga_0_Intel_StrataFlash_Mem_A_pin<8>” LOC = “b12” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<9>” LOC = “a12” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<10>” LOC = “c10” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<11>” LOC = “d10” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<12>” LOC = “h11” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<13>” LOC = “h12” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<14>” LOC = “d11” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<15>” LOC = “e14” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<16>” LOC = “e11” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<17>” LOC = “f14” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<18>” LOC = “f11” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<19>” LOC = “f12” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<20>” LOC = “f16” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<21>” LOC = “g11” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<22>” LOC = “d17” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<23>” LOC = “g12” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<24>” LOC = “h13” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<25>” LOC = “g13” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<26>” LOC = “g14” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<27>” LOC = “h14” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<28>” LOC = “g15” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<29>” LOC = “h15” ; NET “fpga_0_Intel_StrataFlash_Mem_A_pin<30>” LOC = “g17” ; #this pin is in the schematic Flash_A0!

# start Data Bus Flash 0 NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<0>” LOC = “d25” ; #this pin is in the schematic Flash_D0_15! NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<1>” LOC = “e24” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<2>” LOC = “e23” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<3>” LOC = “f21” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<4>” LOC = “a21” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<5>” LOC = “d20” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<6>” LOC = “f20” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<7>” LOC = “g18” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<8>” LOC = “b20” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<9>” LOC = “h24” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<10>” LOC = “h23” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<11>” LOC = “e21” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<12>” LOC = “e20” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<13>” LOC = “a20” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<14>” LOC = “g19” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<15>” LOC = “f18” ; #this pin is in the schematic Flash_D0_0!

# start Data Bus Flash 1 NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<16>” LOC = “a3” ; #this pin is in the schematic Flash_D1_15! NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<17>” LOC = “a4” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<18>” LOC = “a5” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<19>” LOC = “a6” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<20>” LOC = “a7” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<21>” LOC = “a8” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<22>” LOC = “e5” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<23>” LOC = “c5” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<24>” LOC = “b4” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<25>” LOC = “b5” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<26>” LOC = “b6” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<27>” LOC = “b7” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<28>” LOC = “b8” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<29>” LOC = “c4” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<30>” LOC = “d5” ; NET “fpga_0_Intel_StrataFlash_Mem_DQ_pin<31>” LOC = “e6” ; #this pin is in the schematic Flash_D1_0!

#start Flash control signals NET “fpga_0_Intel_StrataFlash_Mem_RPN_pin” LOC = “f15” ; NET “fpga_0_Intel_StrataFlash_Mem_WEN_pin” LOC = “b3” ; NET “fpga_0_Intel_StrataFlash_Mem_OEN_pin” LOC = “b21” ; NET “fpga_0_Intel_StrataFlash_Mem_BYTEn_pin” LOC = “h16” ; NET “fpga_0_Intel_StrataFlash_Mem_CEN_pin<0>” LOC = “e15” ;

#DDR SDRAM 0 #here we change the bit order from big-endian (OPB like) #to little-endian (as it is requested by the ddr ram)

#start DDR SDRAM 0 clock pins NET “fpga_0_Micron_DDR_0_DDR_CKE_pin<0>” LOC = “w5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Clk_pin<0>” LOC = “w1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Clkn_pin<0>” LOC = “w2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_CLK_FB_pin” LOC = “ae14” ;

#start DDR SDRAM 0 address bus and control signals NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<0>” LOC = “v3” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A0_13! NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<1>” LOC = “w6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<2>” LOC = “w7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<3>” LOC = “t6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<4>” LOC = “ad1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<5>” LOC = “ad2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<6>” LOC = “ac1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<7>” LOC = “ab3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<8>” LOC = “ab4” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<9>” LOC = “t8” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<10>” LOC = “r8” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<11>” LOC = “p7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<12>” LOC = “r7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_Addr_pin<13>” LOC = “p6” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A0_0!

NET “fpga_0_Micron_DDR_0_DDR_BankAddr_pin<0>” LOC = “u6” | IOSTANDARD = SSTL2_II ; #BA0_1 NET “fpga_0_Micron_DDR_0_DDR_BankAddr_pin<1>” LOC = “v5” | IOSTANDARD = SSTL2_II ; #BA0_0

NET “fpga_0_Micron_DDR_0_DDR_DQS_pin<0>” LOC = “w4” | IOSTANDARD = SSTL2_II ; #UDQS0 NET “fpga_0_Micron_DDR_0_DDR_DQS_pin<1>” LOC = “r1” | IOSTANDARD = SSTL2_II ; #LDQS0

NET “fpga_0_Micron_DDR_0_DDR_CASn_pin” LOC = “u7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_RASn_pin” LOC = “v6” | IOSTANDARD = SSTL2_II ;

NET “fpga_0_Micron_DDR_0_DDR_CSn_pin<0>” LOC = “v7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_WEn_pin” LOC = “t7” | IOSTANDARD = SSTL2_II ;

# start DDR SDRAM 0 data bus NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<0>” LOC = “p5” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D0_15! NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<1>” LOC = “p4” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<2>” LOC = “r6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<3>” LOC = “r5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<4>” LOC = “t4” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<5>” LOC = “t5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<6>” LOC = “u3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<7>” LOC = “u5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<8>” LOC = “u1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<9>” LOC = “u2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<10>” LOC = “t1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<11>” LOC = “p2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<12>” LOC = “r3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<13>” LOC = “t2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<14>” LOC = “p8” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_0_DDR_DQ_pin<15>” LOC = “p3” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D0_0!

NET “fpga_0_Micron_DDR_0_DDR_DM_pin<0>” LOC = “v4” | IOSTANDARD = SSTL2_II ; #UDM0 NET “fpga_0_Micron_DDR_0_DDR_DM_pin<1>” LOC = “v2” | IOSTANDARD = SSTL2_II ; #LDM0

#DDR SDRAM 1 #here we change the bit order from big-endian (OPB like) #to little-endian (as it is requested by the ddr ram)

#start DDR SDRAM 1 clock pins NET “fpga_0_Micron_DDR_1_DDR_CKE_pin<0>” LOC = “n4” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Clk_pin<0>” LOC = “f5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Clkn_pin<0>” LOC = “f6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_CLK_FB_pin” LOC = “c14” ;

#start DDR SDRAM 1 address bus and control signals NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<0>” LOC = “k5” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A1_13! NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<1>” LOC = “n3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<2>” LOC = “n2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<3>” LOC = “n5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<4>” LOC = “m5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<5>” LOC = “n7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<6>” LOC = “n6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<7>” LOC = “n8” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<8>” LOC = “m1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<9>” LOC = “l1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<10>” LOC = “m2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<11>” LOC = “k1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<12>” LOC = “m3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_Addr_pin<13>” LOC = “l2” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic A1_0!

NET “fpga_0_Micron_DDR_1_DDR_BankAddr_pin<0>” LOC = “j2” | IOSTANDARD = SSTL2_II ; #BA1_1 NET “fpga_0_Micron_DDR_1_DDR_BankAddr_pin<1>” LOC = “k3” | IOSTANDARD = SSTL2_II ; #BA1_0

NET “fpga_0_Micron_DDR_1_DDR_DQS_pin<0>” LOC = “h2” | IOSTANDARD = SSTL2_II ; #UDQS1 NET “fpga_0_Micron_DDR_1_DDR_DQS_pin<1>” LOC = “l7” | IOSTANDARD = SSTL2_II ; #LDQS1

NET “fpga_0_Micron_DDR_1_DDR_CASn_pin” LOC = “k4” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_RASn_pin” LOC = “j4” | IOSTANDARD = SSTL2_II ;

NET “fpga_0_Micron_DDR_1_DDR_CSn_pin<0>” LOC = “m8” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_WEn_pin” LOC = “l4” | IOSTANDARD = SSTL2_II ;

# start DDR SDRAM 0 data bus NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<0>” LOC = “e4” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D1_15! NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<1>” LOC = “e3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<2>” LOC = “d2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<3>” LOC = “h4” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<4>” LOC = “h3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<5>” LOC = “g2” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<6>” LOC = “g1” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<7>” LOC = “j3” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<8>” LOC = “m6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<9>” LOC = “m7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<10>” LOC = “j5” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<11>” LOC = “j6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<12>” LOC = “k6” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<13>” LOC = “j7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<14>” LOC = “k7” | IOSTANDARD = SSTL2_II ; NET “fpga_0_Micron_DDR_1_DDR_DQ_pin<15>” LOC = “l6” | IOSTANDARD = SSTL2_II ; #this pin is in the schematic D1_0!

NET “fpga_0_Micron_DDR_1_DDR_DM_pin<0>” LOC = “k2” | IOSTANDARD = SSTL2_II ; #UDM1 NET “fpga_0_Micron_DDR_1_DDR_DM_pin<1>” LOC = “l5” | IOSTANDARD = SSTL2_II ; #LDM1

# Pins on the system bus. Refer to the system bus documentation for the function of the pins # here all pins where used as GPIO pins with 4 GPIO contoler IP cores NET “GPIO0_GPIO2_IO_pin<0>” LOC = “af23” ; NET “GPIO0_GPIO2_IO_pin<1>” LOC = “af24” ; NET “GPIO0_GPIO2_IO_pin<2>” LOC = “af21” ; NET “GPIO0_GPIO2_IO_pin<3>” LOC = “ad22” ; NET “GPIO0_GPIO2_IO_pin<4>” LOC = “ad23” ; NET “GPIO0_GPIO2_IO_pin<5>” LOC = “ab26” ; NET “GPIO0_GPIO2_IO_pin<6>” LOC = “aa26” ; NET “GPIO0_GPIO2_IO_pin<7>” LOC = “w26” ; NET “GPIO0_GPIO2_IO_pin<8>” LOC = “u26” ; NET “GPIO0_GPIO2_IO_pin<9>” LOC = “t26” ; NET “GPIO0_GPIO2_IO_pin<10>” LOC = “r26” ; NET “GPIO0_GPIO2_IO_pin<11>” LOC = “ab14” ; NET “GPIO0_GPIO2_IO_pin<12>” LOC = “aa13” ; NET “GPIO0_GPIO2_IO_pin<13>” LOC = “p26” ; NET “GPIO0_GPIO2_IO_pin<14>” LOC = “n26” ; NET “GPIO0_GPIO2_IO_pin<15>” LOC = “m26” ; NET “GPIO0_GPIO2_IO_pin<16>” LOC = “c8” ; NET “GPIO0_GPIO2_IO_pin<17>” LOC = “d8” ; NET “GPIO0_GPIO2_IO_pin<18>” LOC = “l26” ; NET “GPIO0_GPIO2_IO_pin<19>” LOC = “d9” ; NET “GPIO0_GPIO2_IO_pin<20>” LOC = “e9” ; NET “GPIO0_GPIO2_IO_pin<21>” LOC = “c9” ; NET “GPIO0_GPIO2_IO_pin<22>” LOC = “b9” ; NET “GPIO0_GPIO2_IO_pin<23>” LOC = “k26” ; NET “GPIO0_GPIO2_IO_pin<24>” LOC = “m21” ; NET “GPIO0_GPIO2_IO_pin<25>” LOC = “m24” ; NET “GPIO0_GPIO2_IO_pin<26>” LOC = “l22” ; NET “GPIO0_GPIO2_IO_pin<27>” LOC = “j24” ; NET “GPIO0_GPIO2_IO_pin<28>” LOC = “f8” ; NET “GPIO0_GPIO2_IO_pin<29>” LOC = “g22” ; NET “GPIO0_GPIO2_IO_pin<30>” LOC = “h26” ; NET “GPIO0_GPIO2_IO_pin<31>” LOC = “h25” ;

NET “GPIO0_GPIO_IO_pin<0>” LOC = “ae24” ; NET “GPIO0_GPIO_IO_pin<1>” LOC = “af20” ; NET “GPIO0_GPIO_IO_pin<2>” LOC = “ad21” ; NET “GPIO0_GPIO_IO_pin<3>” LOC = “ae21” ; NET “GPIO0_GPIO_IO_pin<4>” LOC = “ab21” ; NET “GPIO0_GPIO_IO_pin<5>” LOC = “y23” ; NET “GPIO0_GPIO_IO_pin<6>” LOC = “y22” ; NET “GPIO0_GPIO_IO_pin<7>” LOC = “v23” ; NET “GPIO0_GPIO_IO_pin<8>” LOC = “v24” ; NET “GPIO0_GPIO_IO_pin<9>” LOC = “v25” ; NET “GPIO0_GPIO_IO_pin<10>” LOC = “u23” ; NET “GPIO0_GPIO_IO_pin<11>” LOC = “u24” ; NET “GPIO0_GPIO_IO_pin<12>” LOC = “u25” ; NET “GPIO0_GPIO_IO_pin<13>” LOC = “t23” ; NET “GPIO0_GPIO_IO_pin<14>” LOC = “t25” ; NET “GPIO0_GPIO_IO_pin<15>” LOC = “t22” ; NET “GPIO0_GPIO_IO_pin<16>” LOC = “t21” ; NET “GPIO0_GPIO_IO_pin<17>” LOC = “r25” ; NET “GPIO0_GPIO_IO_pin<18>” LOC = “r24” ; NET “GPIO0_GPIO_IO_pin<19>” LOC = “p23” ; NET “GPIO0_GPIO_IO_pin<20>” LOC = “p25” ; NET “GPIO0_GPIO_IO_pin<21>” LOC = “p24” ; NET “GPIO0_GPIO_IO_pin<22>” LOC = “n23” ; NET “GPIO0_GPIO_IO_pin<23>” LOC = “n25” ; NET “GPIO0_GPIO_IO_pin<24>” LOC = “n24” ; NET “GPIO0_GPIO_IO_pin<25>” LOC = “m25” ; NET “GPIO0_GPIO_IO_pin<26>” LOC = “m22” ; NET “GPIO0_GPIO_IO_pin<27>” LOC = “l21” ; NET “GPIO0_GPIO_IO_pin<28>” LOC = “e8” ; NET “GPIO0_GPIO_IO_pin<29>” LOC = “g8” ; NET “GPIO0_GPIO_IO_pin<30>” LOC = “f25” ; NET “GPIO0_GPIO_IO_pin<31>” LOC = “e26” ;

NET “GPIO1_GPIO2_IO_pin<0>” LOC = “g26” ; NET “GPIO1_GPIO2_IO_pin<1>” LOC = “f26” ; NET “GPIO1_GPIO2_IO_pin<2>” LOC = “g25” ; NET “GPIO1_GPIO2_IO_pin<3>” LOC = “f19” ; NET “GPIO1_GPIO2_IO_pin<4>” LOC = “f17” ; NET “GPIO1_GPIO2_IO_pin<5>” LOC = “c17” ; NET “GPIO1_GPIO2_IO_pin<6>” LOC = “e16” ; NET “GPIO1_GPIO2_IO_pin<7>” LOC = “c15” ; NET “GPIO1_GPIO2_IO_pin<8>” LOC = “d14” ; NET “GPIO1_GPIO2_IO_pin<9>” LOC = “f13” ; NET “GPIO1_GPIO2_IO_pin<10>” LOC = “c23” ; NET “GPIO1_GPIO2_IO_pin<11>” LOC = “a23” ; NET “GPIO1_GPIO2_IO_pin<12>” LOC = “b23” ; NET “GPIO1_GPIO2_IO_pin<13>” LOC = “a22” ; NET “GPIO1_GPIO2_IO_pin<14>” LOC = “b22” ; NET “GPIO1_GPIO2_IO_pin<15>” LOC = “d19” ; NET “GPIO1_GPIO2_IO_pin<16>” LOC = “b19” ; NET “GPIO1_GPIO2_IO_pin<17>” LOC = “c18” ; NET “GPIO1_GPIO2_IO_pin<18>” LOC = “d18” ; NET “GPIO1_GPIO2_IO_pin<19>” LOC = “b17” ; NET “GPIO1_GPIO2_IO_pin<20>” LOC = “b16” ; NET “GPIO1_GPIO2_IO_pin<21>” LOC = “a14” ; NET “GPIO1_GPIO2_IO_pin<22>” LOC = “c22” ; NET “GPIO1_GPIO2_IO_pin<23>” LOC = “c25” ; NET “GPIO1_GPIO2_IO_pin<24>” LOC = “d26” ; NET “GPIO1_GPIO2_IO_pin<25>” LOC = “h20” ; NET “GPIO1_GPIO2_IO_pin<26>” LOC = “u22” ; NET “GPIO1_GPIO2_IO_pin<27>” LOC = “r20” ; NET “GPIO1_GPIO2_IO_pin<28>” LOC = “aa18” ; NET “GPIO1_GPIO2_IO_pin<29>” LOC = “w20” ; NET “GPIO1_GPIO2_IO_pin<30>” LOC = “u20” ; NET “GPIO1_GPIO2_IO_pin<31>” LOC = “u21” ;

NET “GPIO1_GPIO_IO_pin<0>” LOC = “f24” ; NET “GPIO1_GPIO_IO_pin<1>” LOC = “e25” ; NET “GPIO1_GPIO_IO_pin<2>” LOC = “f23” ; NET “GPIO1_GPIO_IO_pin<3>” LOC = “e22” ; NET “GPIO1_GPIO_IO_pin<4>” LOC = “e19” ; NET “GPIO1_GPIO_IO_pin<5>” LOC = “e18” ; NET “GPIO1_GPIO_IO_pin<6>” LOC = “e17” ; NET “GPIO1_GPIO_IO_pin<7>” LOC = “d16” ; NET “GPIO1_GPIO_IO_pin<8>” LOC = “k21” ; NET “GPIO1_GPIO_IO_pin<9>” LOC = “k20” ; NET “GPIO1_GPIO_IO_pin<10>” LOC = “b15” ; NET “GPIO1_GPIO_IO_pin<11>” LOC = “j21” ; NET “GPIO1_GPIO_IO_pin<12>” LOC = “j20” ; NET “GPIO1_GPIO_IO_pin<13>” LOC = “h21” ; NET “GPIO1_GPIO_IO_pin<14>” LOC = “c21” ; NET “GPIO1_GPIO_IO_pin<15>” LOC = “c19” ; NET “GPIO1_GPIO_IO_pin<16>” LOC = “a19” ; NET “GPIO1_GPIO_IO_pin<17>” LOC = “b18” ; NET “GPIO1_GPIO_IO_pin<18>” LOC = “a17” ; NET “GPIO1_GPIO_IO_pin<19>” LOC = “a16” ; NET “GPIO1_GPIO_IO_pin<20>” LOC = “a15” ; NET “GPIO1_GPIO_IO_pin<21>” LOC = “d21” ; NET “GPIO1_GPIO_IO_pin<22>” LOC = “d22” ; NET “GPIO1_GPIO_IO_pin<23>” LOC = “c26” ; NET “GPIO1_GPIO_IO_pin<24>” LOC = “g20” ; NET “GPIO1_GPIO_IO_pin<25>” LOC = “g21” ; NET “GPIO1_GPIO_IO_pin<26>” LOC = “w21” ; NET “GPIO1_GPIO_IO_pin<27>” LOC = “v21” ; NET “GPIO1_GPIO_IO_pin<28>” LOC = “aa20” ; NET “GPIO1_GPIO_IO_pin<29>” LOC = “y18” ; NET “GPIO1_GPIO_IO_pin<30>” LOC = “v20” ; NET “GPIO1_GPIO_IO_pin<31>” LOC = “y17” ;

NET “GPIO2_GPIO2_IO_pin<0>” LOC = “ae20” ; NET “GPIO2_GPIO2_IO_pin<1>” LOC = “ae18” ; NET “GPIO2_GPIO2_IO_pin<2>” LOC = “ae23” ; NET “GPIO2_GPIO2_IO_pin<3>” LOC = “af22” ; NET “GPIO2_GPIO2_IO_pin<4>” LOC = “ae22” ; NET “GPIO2_GPIO2_IO_pin<5>” LOC = “ab25” ; NET “GPIO2_GPIO2_IO_pin<6>” LOC = “aa25” ; NET “GPIO2_GPIO2_IO_pin<7>” LOC = “ac19” ; NET “GPIO2_GPIO2_IO_pin<8>” LOC = “ab17” ; NET “GPIO2_GPIO2_IO_pin<9>” LOC = “r22” ; NET “GPIO2_GPIO2_IO_pin<10>” LOC = “p22” ; NET “GPIO2_GPIO2_IO_pin<11>” LOC = “n22” ; NET “GPIO2_GPIO2_IO_pin<12>” LOC = “k22” ; NET “GPIO2_GPIO2_IO_pin<13>” LOC = “t19” ; NET “GPIO2_GPIO2_IO_pin<14>” LOC = “p20” ; NET “GPIO2_GPIO2_IO_pin<15>” LOC = “n20” ; NET “GPIO2_GPIO2_IO_pin<16>” LOC = “m20” ; NET “GPIO2_GPIO2_IO_pin<17>” LOC = “l20” ; NET “GPIO2_GPIO2_IO_pin<18>” LOC = “l25” ; NET “GPIO2_GPIO2_IO_pin<19>” LOC = “k25” ; NET “GPIO2_GPIO2_IO_pin<20>” LOC = “j25” ; NET “GPIO2_GPIO2_IO_pin<21>” LOC = “j22” ; NET “GPIO2_GPIO2_IO_pin<22>” LOC = “g23” ; NET “GPIO2_GPIO2_IO_pin<23>” LOC = “b11” ; NET “GPIO2_GPIO2_IO_pin<24>” LOC = “a11” ; NET “GPIO2_GPIO2_IO_pin<25>” LOC = “y25” ; NET “GPIO2_GPIO2_IO_pin<26>” LOC = “aa22” ; NET “GPIO2_GPIO2_IO_pin<27>” LOC = “ab23” ; NET “GPIO2_GPIO2_IO_pin<28>” LOC = “ab22” ; NET “GPIO2_GPIO2_IO_pin<29>” LOC = “ac25” ; NET “GPIO2_GPIO2_IO_pin<30>” LOC = “w23” ; NET “GPIO2_GPIO2_IO_pin<31>” LOC = “v22” ;

NET “GPIO2_GPIO_IO_pin<0>” LOC = “af19” ; NET “GPIO2_GPIO_IO_pin<1>” LOC = “ad19” ; NET “GPIO2_GPIO_IO_pin<2>” LOC = “ac21” ; NET “GPIO2_GPIO_IO_pin<3>” LOC = “ac22” ; NET “GPIO2_GPIO_IO_pin<4>” LOC = “ab20” ; NET “GPIO2_GPIO_IO_pin<5>” LOC = “ab19” ; NET “GPIO2_GPIO_IO_pin<6>” LOC = “aa24” ; NET “GPIO2_GPIO_IO_pin<7>” LOC = “ac20” ; NET “GPIO2_GPIO_IO_pin<8>” LOC = “ab18” ; NET “GPIO2_GPIO_IO_pin<9>” LOC = “t20” ; NET “GPIO2_GPIO_IO_pin<10>” LOC = “r21” ; NET “GPIO2_GPIO_IO_pin<11>” LOC = “p21” ; NET “GPIO2_GPIO_IO_pin<12>” LOC = “n21” ; NET “GPIO2_GPIO_IO_pin<13>” LOC = “l23” ; NET “GPIO2_GPIO_IO_pin<14>” LOC = “r19” ; NET “GPIO2_GPIO_IO_pin<15>” LOC = “p19” ; NET “GPIO2_GPIO_IO_pin<16>” LOC = “n19” ; NET “GPIO2_GPIO_IO_pin<17>” LOC = “m19” ; NET “GPIO2_GPIO_IO_pin<18>” LOC = “l19” ; NET “GPIO2_GPIO_IO_pin<19>” LOC = “k23” ; NET “GPIO2_GPIO_IO_pin<20>” LOC = “k24” ; NET “GPIO2_GPIO_IO_pin<21>” LOC = “j23” ; NET “GPIO2_GPIO_IO_pin<22>” LOC = “h22” ; NET “GPIO2_GPIO_IO_pin<23>” LOC = “b10” ; NET “GPIO2_GPIO_IO_pin<24>” LOC = “a10” ; NET “GPIO2_GPIO_IO_pin<25>” LOC = “y26” ; NET “GPIO2_GPIO_IO_pin<26>” LOC = “aa21” ; NET “GPIO2_GPIO_IO_pin<27>” LOC = “ab24” ; NET “GPIO2_GPIO_IO_pin<28>” LOC = “ac26” ; NET “GPIO2_GPIO_IO_pin<29>” LOC = “w24” ; NET “GPIO2_GPIO_IO_pin<30>” LOC = “w25” ; NET “GPIO2_GPIO_IO_pin<31>” LOC = “w22” ;

NET “GPIO3_GPIO_IO_pin<0>” LOC = “ad25” ;

# These pins are declared as prohibit because they are not available on small Spartan3 FPGAs like the xc3s1500 and xc3s1000 # the on-board peripherals don't use these pins. a small amount of GPIO pins is not available on the xc3s1000 CONFIG PROHIBIT = G7; CONFIG PROHIBIT = G6; CONFIG PROHIBIT = E2; CONFIG PROHIBIT = E1; CONFIG PROHIBIT = F4; CONFIG PROHIBIT = F3; CONFIG PROHIBIT = G5; CONFIG PROHIBIT = G4; CONFIG PROHIBIT = F2; CONFIG PROHIBIT = F1; CONFIG PROHIBIT = H7; CONFIG PROHIBIT = H6; CONFIG PROHIBIT = Y1; CONFIG PROHIBIT = Y2; CONFIG PROHIBIT = AA1; CONFIG PROHIBIT = AA2; CONFIG PROHIBIT = Y4; CONFIG PROHIBIT = Y5; CONFIG PROHIBIT = AA3; CONFIG PROHIBIT = AA4; CONFIG PROHIBIT = Y6; CONFIG PROHIBIT = Y7; CONFIG PROHIBIT = AB1; CONFIG PROHIBIT = AB2; CONFIG PROHIBIT = AA23; CONFIG PROHIBIT = Y21; CONFIG PROHIBIT = Y20; CONFIG PROHIBIT = AA8; CONFIG PROHIBIT = AB8; CONFIG PROHIBIT = AC8; CONFIG PROHIBIT = AD8; CONFIG PROHIBIT = AC9; CONFIG PROHIBIT = AD9; CONFIG PROHIBIT = AE9; CONFIG PROHIBIT = AE10; CONFIG PROHIBIT = AF10; CONFIG PROHIBIT = AE11; CONFIG PROHIBIT = AF11; CONFIG PROHIBIT = AF16; CONFIG PROHIBIT = AE16; CONFIG PROHIBIT = AF17; CONFIG PROHIBIT = AE17; CONFIG PROHIBIT = AD18; CONFIG PROHIBIT = AC18; CONFIG PROHIBIT = AA19; CONFIG PROHIBIT = Y19;