Project details

Maintainer orphaned
Revision: unknown
Development status: stable
Compatibility: GECKO3


 Contributed by the Ilmenau University of Technology, Ilmenau, Germany

This page introduces the GECKO3STACK - a system combining several gecko3main modules to an FPGA array.


GECKO3 staddle

The GECKO3STACK is built on the gecko3_staddle platform, which provides power supply, JTAG facilities and user interface ports. With a GECKO3 staddle a stack of up to five modules can be built.

Connection between the modules is realized as a physical bus over the system bus connectors. On the IO1 BUS connector the pins supporting the Altium soft-JTAG chain are reserved and an external clock pin can be utilized as a global bus clock. The unassigned pins can be used arbitrarily, or to access the user interface features of the staddle. On the connector IO2 BUS up to 116 pins are available to implement inter-module communication.

 Pin assignment

To operate a GECKO3STACK, first the required number of GECKO3main modules have to be placed on the GECKO3 stadde platform. Second, it has to be made sure, that the jumpers for the power supply are set to Extern, before a 12V external power source can be connected to the front panel.

 JTAG bridge cable

To prepare the JTAG connection to the stack, select the number of nodes with the slide switch and connect all the GECKO3main modules' JTAG interfaces consecutively to the 8-pin headers on the staddle. Since the GECKO3 staddle platform is laid out for both, the GECKO3STACK can be set up for development using either the Xilinx ISE or the Altium Designer tool suite. A self-tailored JTAG bridge cable can be used for both options.

Xilinx ISE

 Xilinx Platform Cable USB II Developing with the Xilinx tools requires the connection with a Xilinx Platform Cable. The number of nodes has been set by the slide switch, but the DIP-switches have to be set on disable, since the Xilinx tools do not utilize the soft-JTAG feature. Therefore, also the respective pins of the JTAG bridge cable do not have to be connected to the modules RS232 header. Commonly, projects for each GECKO3main module are programmed to the FPGAs using iMPACT, the Boundary scan view of which should show all Spartan3s connected by the JTAG chain.

Xilinx iMPACT Boundary Scan view

Altium Designer

 Cool new Altium USB JTAG adapter ;) Setting up the stack for development with Altium Designer requires the connection with the Altium USB JTAG Adapter using the designated port on the staddle. Additionally to selecting the number of nodes in the stack by the slide switch, the DIP switches can be used to enable the respective node for the utilization of the Altium Soft-JTAG chain. The associated pins of the JTAG bridge cable have to be connected to the (now converted) RS232 header. The soft-chain interface has to be included in the FPGA designs, as do the soft-JTAG instruments. These instruments, e.g. logic analysers, show up as devices on an additional JTAG chain in Altium Designer's Devices view pane, from which they can also be accessed during runtime.

 Altium Designer Devices view with Soft-JTAG devices

For designs with Altium soft-JTAG devices the use of this adapted constraint file is required (it includes the mappings of the soft-JTAG signals to both the original RS232-header, and to GPIO-bus pins for distribution throughout the stack).

As in any distributed system, in a GECKO3STACK an application will partitioned and implemented on several processing nodes, so providing an efficient inter-module communication is crucial. Data transfer between the nodes can be realized in different ways, depending on the requirements of the distributed application. For only weakly connected application components routing the signals directly over the physical bus connectors could be sufficient. But, in order to utilize more generic and flexible means of communication, dedicated interface components implementing various communication methods and protocols can be provided.

 Shared memory idea

The idea of communicating via shared memory is the exchange of data over a global memory, that is equally and independently accessible by all nodes.

SHIVA - SHared memory Interface for Versatile Application

SHIVA is a component to realize shared memory communication within a GECKO3STACK, without using an actual dedicated memory element. Instead, the internal resources of the FPGAs on the GECKO3main modules will be used to create a distributed shared memory. Central concept is to unify sections of the local BRAM on every connected Spartan3 in a global address space. This virtually global memory is established by the interface component SHIVA. The partial application on each FPGA will thus access data over a global address, independently of the actual physical memory location, and, more importantly, independently from the actual physical bus communication.

 Distributed shared memory concept


FIXME Details on SHIVA will be discussed separately.

  • gecko-systems/gecko3stack/start.txt
  • Last modified: 2020/09/09 14:25
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