GECKO3analog [beta]

The GECKO3analog Board provides an audio codec, a 8-channel analog to digital converter and a 8-channel digital to analog converter. It could be used for digital audio processing and digital signal processing with access to the analog world in both directions.

Blockdiagram for GECKO3analog

positions of the switch

  • The reference voltage of -2.5 V, needed to provide a bipolar DAC output, is not active by default. To activate the reference, you have to change the configuration of the DAC and activate his internal reference. Then an OPAMP invert the +2.5 V reference to -2.5 V. (For the activation of the internal reference in the DAC. (See page 31 of the data sheet)
  • Be sure that the switch is on position 1 if you want to use the standard bus position. (SeeGECKO3 system bus for more informations)
  • Have a look at the schematic to see how the IC's are connected to the FPGA. (Schematics)
Pin (I/O) Block Name (FPGA / analog) Pin (on chip) Description
Audio CODEC I2S - Interface
25 / 67 B5.0 / B18.0 GPIO1_16 / GPIO2_64 / COD_DACLRC 5 DAC Sample Rate Left/Right Clock
28 / 68 B5.1 / B18.1 GPIO1_17 / GPIO2_65 / COD_DACDAT 4 DAC Digital Audio Data Input
27 / 69 B5.2 / B18.2 GPIO1_18 / GPIO2_66 / COD_ADCDAT 6 ADC Digital Audio Data Output
84 / 70 B5.3 / B18.3 GPIO1_19 / GPIO2_67 / COD_ADCLRC 7 ADC Sample Rate Left/Right Clock
85 / 71 B5.4 / B18.4 GPIO1_20 / GPIO2_68 / COD_BCLK 3 Digital Audio Bit Clock
Audio CODEC SPI - Interface
86 / 72 B5.5 / B18.5 GPIO1_21 / GPIO2_69 / COD_CSB 22 3-Wire MPU Chip Select / SPI chip select
87 / 73 B5.6 / B18.6 GPIO1_22 / GPIO2_70 / COD_SDIN 23 3-Wire MPU Data Input / SPI MOSI
88 / 74 B5.7 / B18.7 GPIO1_23 / GPIO2_71 / COD_SCLK 24 3-Wire MPU Clock Input / SPI CLK
Audio CODEC Clock Output
91 / 75 B6.0 / B19.0 GPIO1_24 / GPIO2_72 / COD_CLKOUT 2 Buffered Clock Output
ADC - Interface
92 / 76 B6.1 / B19.1 GPIO1_25 / GPIO2_73 / ADC_CS 8 Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is disabled to clock data, but works as conversion clock source if programmed. The falling edge of CS input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from high-impedance state.
If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave select (SS) to provide an SPI interface.
If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip select to allow host to access the individual converter.
93 / 77 B6.2 / B19.2 GPIO1_26 / GPIO2_74 / ADC_FS 2 Frame sync input from DSP. The rising edge of FS indicates the start of a serial data frame being transferred (coming into or being sent out of the device). If FS is low at the falling edge of CS, the rising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI, SDO, and SCLK. Tie this pin to DVDD if FS is not used to initiate the operation cycle.
94 / 78 B6.3 / B19.3 GPIO1_27 / GPIO2_75 / ADC_SCLK 1 Serial clock input from the host processor to clock in the input from SDI and clock out the output via SDO. It can also be used as the conversion clock source when the external conversion clock is selected (see Table 2). When CS is low, SCLK is enabled. When CS is high, SCLK is disabled for the data transfer, but can still work as the conversion clock source.
95 / 79 B6.4 / B19.4 GPIO1_28 / GPIO2_76 / ADC_SDI 3 Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits, except for the WRITE CFR command, are filled with zeros. The WRITE CFR command requires additional 12-bit data. The MSB of input data, ID(15), is latched at the first falling edge of SCLK following FS falling edge if FS starts the operation, or latched at the falling edge of first SCLK following CS falling edge when CS initiates the operation.
The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the falling edge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS, whichever happens first. Refer to the timing specification for the timing requirements. Tie SDI to DVDD if using hardware default mode (refer to Device Initialization).
96 / 80 B6.5 / B19.5 GPIO1_29 / GPIO2_77 / ADC_SDO 5 The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO. SDO is in the high-impedance state when CS is high. SDO is released after a CS falling edge. The output format is MSB (OD15) first.
When FS initiates the operation, the MSB of output via SDO, OD(15), is valid before the first falling edge of SCLK following the falling edge of FS.
When CS initiates the operation, the MSB, OD(15), is valid before the first falling edge of SCLK following the CS falling edge.
The remaining data bits (if any) are shifted out on the rising edge of SCLK and are valid before the falling edge of SCLK. Refer to the timing specification for the details.
In select/conversion operation, the first 14 bits are the results from the previous conversion (data). In a READ FIFO operation, this data is from FIFO. In both cases, the last two bits are don’t care.
In a WRITE operation, the output from SDO must be ignored.\\SDO goes into high-impedance state at the 16th falling edge of SCLK after the operation cycle is initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11.
97 / 81 B6.6 / B19.6 GPIO1_30 / GPIO2_78 / ADC_CSTART 24 External sampling trigger signal, which initiates the sampling from a selected analog input channel when the device works in extended sampling mode (asynchronous sampling). A high-to-low transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold mode and starts the conversion. The low time of the CSTART signal controls the sampling period. CSTART signal must stay low long enough for proper sampling. CSTART must stay high long enough after the low-to-high transition for the conversion to finish maturely. The activation of CSTART is independent of SCLK and the level of CS and FS. However, the first CSTART cannot be issued before the rising edge of the eleventh SCLK. Tie this pin to DVDD if not used.
98 / 82 B6.7 / B19.7 GPIO1_31 / GPIO2_79 / ADC_EOC/INT 4 End of conversion (EOC) or interrupt to host processor (INT)
EOC: used in conversion mode 00 only. EOC goes from high to low at the end of the sampling and remains low until the conversion is complete and data is ready.
INT: Interrupt to the host processor. The falling edge of INT indicates data is ready for output. INT is cleared by the following CS↓, FS↑, or CSTART↓.
DAC - Interface
99 / 83 B7.0 / B20.0 GPIO1_32 / GPIO2_80 / DAC_SYNC 2 Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 32nd clock. If SYNC is taken high before the 31st clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC8168. Schmitt-Trigger logic input.
100 / 84 B7.1 / B20.1 GPIO1_33 / GPIO2_81 / DAC_DIN 15 Serial data input. Data are clocked into the 32-bit input shift register on each falling edge of the serial clock input. Schmitt-Trigger logic input.
101 / 85 B7.2 / B20.2 GPIO1_34 / GPIO2_82 / DAC_SCLK 16 Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
102 / 86 B7.3 / B20.3 GPIO1_35 / GPIO2_83 / DAC_LDAC 1 Load DACs.
103 / 87 B7.4 / B20.4 GPIO1_36 / GPIO2_84 / DAC_CLR 9 Asynchronous clear input.
104 / 88 B7.5 / B20.5 GPIO1_37 / GPIO2_85 / SIGMA_DELTA Low-pass filtered output for example for a sigma delta converter. Provide a passive 2nd order low-pass filter non amplified and a active low-pass filter, one non amplified and one amplified to +/- 10 V.
105 / 89 B7.6 / B20.6 GPIO1_38 / GPIO2_86 not used
106 / 90 B7.7 / B20.7 GPIO1_39 / GPIO2_87 not used

The audio part provide the following four lines, which could be connected with a 3.5 mm Audio Jack:

  • Mono microphone In (electret microphone)
  • Stereo line in
  • Stereo headphone out
  • Stereo line out

The provided sampling rate is 48 kHz and the resolution is maximum 24 bit.

The selected audio codec is simple to use. The audio datas are transfered on a I2S-Bus and the configuration of the numerous options could be done over a SPI-Bus. The following Figure shows the block scheme of the Audio CODEC.

Block scheme of the Audio CODEC WM8731

The Datasheet of WM8731: WM8731

This part of the board provides in each direction (AD/DA) 8 channels with a maximum sample rate of 200-KSPS. The signal levels are ±10 V and for the communication each chip has an SPI-Bus.

The ADC from Texas Instruments has the following key data:

  • 14-Bit Resolution
  • Maximum Throughput 200-KSPS
  • 8 Single-Ended Channels
  • Analog Input Range: ±10 V
  • Pseudodifferential Analog Inputs
  • SPI/DSP-Compatible Serial Interfaces with SCLK up to 25-MHz
  • Single 5-V Analog Supply; 3-/5-V Digital Supply
  • Low-Power

The data sheet of the ADC: TLC3578

The DAC from Texas Instruments has the following key data:

  • 14-Bit Resolution
  • Relative Accuracy: 1 LSB INL
  • Internal Reference
  • Ultra-Low Power Operation
  • SPI/DSP-Compatible Serial Interfaces with SCLK up to 50-MHz
  • Wide Power-Supply Range: +2.7V to +5.5V

The data sheet of the DAC: DAC8168

The needed supply voltages, which are ±12 V and ±5 V, are generated out of the battery voltage with a step-up dc/dc converter from Linear Technology (LT3471) in combination with linear voltage regulators to have a accurate and a noiseless voltage.

The LT3471 is a dual switching regulator combines two 42V, 1.3A switches with error amplifiers that can sense to ground providing boost and inverting capability.The LT3471 is available in a low profile (0.75mm) 10-lead 3mm × 3mm DFN package.

The data sheet of the LT3471: LT3471

Front of the GECKO3analog

Backside of the GECKO3analog

GECKO3analog on the docking

GECKO3analog on the robot

  • gecko-addons/gecko3analog.txt
  • Last modified: 2021/12/20 10:49
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