gecko-addons:gecko-visual:ip-architecture

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gecko-addons:gecko-visual:ip-architecture [2017/03/10 12:37] – ghj1-localgecko-addons:gecko-visual:ip-architecture [2021/12/20 10:49] (current) – external edit 127.0.0.1
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 This state machine controls the write process to the SDRAM. The write process signaling is shown in the following image: This state machine controls the write process to the SDRAM. The write process signaling is shown in the following image:
 +{{ :gecko-addons:gecko-visual:wiki_npi_write.jpg?600 |}}
  
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 The selected write mode is "8-word cacheline transfer". 1 word corresponds to 32-bit which is equal to 1 pixel. If 8 pixel from the pixel fifo are ready to read(prog empty), the data is read out and written into the fifo of the memory controller. After this an address request is done. If the address request is acknowledged, the address is incremented and the process starts again. The selected write mode is "8-word cacheline transfer". 1 word corresponds to 32-bit which is equal to 1 pixel. If 8 pixel from the pixel fifo are ready to read(prog empty), the data is read out and written into the fifo of the memory controller. After this an address request is done. If the address request is acknowledged, the address is incremented and the process starts again.
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 The display NPI IP-core reads the camera data from the SDRAM and brings the data to the display. The following image shows the architecture of this IP-core: The display NPI IP-core reads the camera data from the SDRAM and brings the data to the display. The following image shows the architecture of this IP-core:
 +{{ :gecko-addons:gecko-visual:wiki_display_npi_complete.png?600 |}}
  
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 == diplay_init.vhd == == diplay_init.vhd ==
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 The pixel data is transferred by the RGB data interface. The display_logig.vhd block reads the pixel fifo and generates the pixel clock as well as the synchronisation signals: The pixel data is transferred by the RGB data interface. The display_logig.vhd block reads the pixel fifo and generates the pixel clock as well as the synchronisation signals:
 +{{ :gecko-addons:gecko-visual:wiki_display_timing.jpg?600 |}}
  
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 The display NPI State Machine controls the read cycles from the SDRAM. The signaling of the read process is shown in the following image: The display NPI State Machine controls the read cycles from the SDRAM. The signaling of the read process is shown in the following image:
- +{{ :gecko-addons:gecko-visual:wiki_npi_read.jpg?600 |}}
-{{:gecko-addons:gecko-visual:wiki_npi_read.jpg?nolink&600 |}}+
  
 After receiving the init done and the running signal the state machine starts to generate read requests. If a read request is accepted the data is taken out and written into the pixel fifo. The data is read in 8-word bursts. After each read cycle the address generation is activated. After receiving the init done and the running signal the state machine starts to generate read requests. If a read request is accepted the data is taken out and written into the pixel fifo. The data is read in 8-word bursts. After each read cycle the address generation is activated.
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  • Last modified: 2021/12/20 10:49
  • (external edit)