gecko-addons:gecko-visual:ip-architecture

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gecko-addons:gecko-visual:ip-architecture [2017/03/10 08:10] – external edit 127.0.0.1gecko-addons:gecko-visual:ip-architecture [2021/12/20 10:49] (current) – external edit 127.0.0.1
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 To test the functionality of all hardware components on the GECKO-visual board the following IP-architecture was realized: To test the functionality of all hardware components on the GECKO-visual board the following IP-architecture was realized:
  
-{{:gecko3:gecko-addon:gecko-visual:wiki_simple_arch.png?nolink&600|}}+{{:gecko-addons:gecko-visual:wiki_simple_arch.png?nolink&600|}}
  
 The IP-architecture is local to the GECKO-visual FPGA and has no link to the GECKO-main. A continuous stream of frames is taken from the camera and buffered into the SDRAM. The buffered data is then read out and displayed by the LCD. Main element of the design is the Xilinx multiport memory controller (mpmc) which controls the read and write accesses from and to the SDRAM. All components (IP-Cores) are discussed in detail in the following sections. The IP-architecture is local to the GECKO-visual FPGA and has no link to the GECKO-main. A continuous stream of frames is taken from the camera and buffered into the SDRAM. The buffered data is then read out and displayed by the LCD. Main element of the design is the Xilinx multiport memory controller (mpmc) which controls the read and write accesses from and to the SDRAM. All components (IP-Cores) are discussed in detail in the following sections.
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 The selected camera resolution is 1.3 MP which corresponds to 1280x960. Each pixel has a data width of 10-bit. The following picture shows the scan direction and order of pixel:  The selected camera resolution is 1.3 MP which corresponds to 1280x960. Each pixel has a data width of 10-bit. The following picture shows the scan direction and order of pixel: 
  
-{{ :gecko3:gecko-addon:gecko-visual:wiki_bayer.png?nolink&200 |}}+{{ :gecko-addons:gecko-visual:wiki_bayer.png?nolink&200 |}}
  
  
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 From the data outputs of odd and even line fifo one single RGB pixel is formed. The red and blue values are copied directly, the green value is generated by the average of both green values. The most significant byte of the pixel data remains empty. The data is then buffered into a 32-bit fifo. From there the data is read and written into the SDRAM. From the data outputs of odd and even line fifo one single RGB pixel is formed. The red and blue values are copied directly, the green value is generated by the average of both green values. The most significant byte of the pixel data remains empty. The data is then buffered into a 32-bit fifo. From there the data is read and written into the SDRAM.
  
-{{ :gecko3:gecko-addon:gecko-visual:wiki_pixel_demosaic.png?nolink&600 |}}+{{ :gecko-addons:gecko-visual:wiki_pixel_demosaic.png?nolink&600 |}}
  
 The described demosaic process results in an image with half the size of the input data. The new image size is 640x480 which is still enough for the display resolutoin (320x480). The described demosaic process results in an image with half the size of the input data. The new image size is 640x480 which is still enough for the display resolutoin (320x480).
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-{{ :gecko3:gecko-addon:gecko-visual:wiki_pixel_read_out.png?nolink&300 |}}+{{ :gecko-addons:gecko-visual:wiki_pixel_read_out.png?nolink&300 |}}
  
  
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 Find all details in the [[http://www.xilinx.com/support/documentation/ip_documentation/mpmc.pdf|mpmc datasheet]].\\ Find all details in the [[http://www.xilinx.com/support/documentation/ip_documentation/mpmc.pdf|mpmc datasheet]].\\
-{{:gecko3:gecko-addon:gecko-visual:ar24912.zip|}} provides an example of an NPI-PCore which performs read and write cycles.+{{:gecko-addons:gecko-visual:ar24912.zip|}} provides an example of an NPI-PCore which performs read and write cycles.
 ---- ----
  
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 The following figure shows a detailed the structure of the Camera NPI:\\ The following figure shows a detailed the structure of the Camera NPI:\\
-{{:gecko3:gecko-addon:gecko-visual:wiki_camera_npi_complete.png?nolink&700|}}+{{:gecko-addons:gecko-visual:wiki_camera_npi_complete.png?nolink&700|}}
  
 == camera_init.vhd == == camera_init.vhd ==
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 This state machine controls the write process to the SDRAM. The write process signaling is shown in the following image: This state machine controls the write process to the SDRAM. The write process signaling is shown in the following image:
 +{{ :gecko-addons:gecko-visual:wiki_npi_write.jpg?600 |}}
  
-{{:huce:microlab:projects:internal:gecko:gecko-addon:gecko-visual:wiki_npi_write.jpg?nolink&600|}} 
  
 The selected write mode is "8-word cacheline transfer". 1 word corresponds to 32-bit which is equal to 1 pixel. If 8 pixel from the pixel fifo are ready to read(prog empty), the data is read out and written into the fifo of the memory controller. After this an address request is done. If the address request is acknowledged, the address is incremented and the process starts again. The selected write mode is "8-word cacheline transfer". 1 word corresponds to 32-bit which is equal to 1 pixel. If 8 pixel from the pixel fifo are ready to read(prog empty), the data is read out and written into the fifo of the memory controller. After this an address request is done. If the address request is acknowledged, the address is incremented and the process starts again.
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 The display NPI IP-core reads the camera data from the SDRAM and brings the data to the display. The following image shows the architecture of this IP-core: The display NPI IP-core reads the camera data from the SDRAM and brings the data to the display. The following image shows the architecture of this IP-core:
 +{{ :gecko-addons:gecko-visual:wiki_display_npi_complete.png?600 |}}
  
-{{ :huce:microlab:projects:internal:gecko:gecko-addon:gecko-visual:wiki_display_npi_complete.png?nolink&650 |}} 
  
 == diplay_init.vhd == == diplay_init.vhd ==
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 The pixel data is transferred by the RGB data interface. The display_logig.vhd block reads the pixel fifo and generates the pixel clock as well as the synchronisation signals: The pixel data is transferred by the RGB data interface. The display_logig.vhd block reads the pixel fifo and generates the pixel clock as well as the synchronisation signals:
 +{{ :gecko-addons:gecko-visual:wiki_display_timing.jpg?600 |}}
  
-{{ :gecko3:gecko-addon:gecko-visual:wiki_display_timing.jpg?nolink&600 |}} 
  
  
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 The display NPI State Machine controls the read cycles from the SDRAM. The signaling of the read process is shown in the following image: The display NPI State Machine controls the read cycles from the SDRAM. The signaling of the read process is shown in the following image:
- +{{ :gecko-addons:gecko-visual:wiki_npi_read.jpg?600 |}}
-{{ :gecko3:gecko-addon:gecko-visual:wiki_npi_read.jpg?nolink&600 |}}+
  
 After receiving the init done and the running signal the state machine starts to generate read requests. If a read request is accepted the data is taken out and written into the pixel fifo. The data is read in 8-word bursts. After each read cycle the address generation is activated. After receiving the init done and the running signal the state machine starts to generate read requests. If a read request is accepted the data is taken out and written into the pixel fifo. The data is read in 8-word bursts. After each read cycle the address generation is activated.
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  • Last modified: 2021/12/20 10:49
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