gecko-platforms:gecko3_staddle

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision		 Previous revision
gecko-platforms:gecko3_staddle [2017/03/10 13:30] – ghj1-localgecko-platforms:gecko3_staddle [2021/12/20 10:49] (current) – external edit 127.0.0.1
Line 38: Line 38:
  
 ===== PS/2 ===== ===== PS/2 =====
-{{:gecko-platforms:gecko3_staddle:staddleps2.jpg?194 |PS/2 ports}}{{ .:bustreiber.png?200|PS/2 port schematic}}+{{:gecko-platforms:gecko3_staddle:staddleps2.jpg?194 |PS/2 ports}}{{ :gecko-platforms:gecko3_staddle:bustreiber.png?200|PS/2 port schematic}}
 There are two PS/2 ports applied to the front panel for user input via keyboard and mouse. The signals are passed through the system bus to the GECKO3main modules. Since both, the input device and the FPGA can drive the line, a short circuit by different signal levels must be prevented. This can be realized using the tri-state outputs of the FPGA, but has to be taken care of by the PS/2 component within the FPGA design. A "zero" is given active to the output, but instead of an active "one", the output is set high impedance (disable). The high level of the line is achieved by the external pull-up resistor to 5 V. There are two PS/2 ports applied to the front panel for user input via keyboard and mouse. The signals are passed through the system bus to the GECKO3main modules. Since both, the input device and the FPGA can drive the line, a short circuit by different signal levels must be prevented. This can be realized using the tri-state outputs of the FPGA, but has to be taken care of by the PS/2 component within the FPGA design. A "zero" is given active to the output, but instead of an active "one", the output is set high impedance (disable). The high level of the line is achieved by the external pull-up resistor to 5 V.
  
Line 62: Line 62:
 Due to the use of continuous areas for equal types of signals, the 18 digital lines to the VGA port are also located in the first section of the IO1 bus. The four signals of the PS2 interfaces are transmitted on lines on the higher connector section. Due to the use of continuous areas for equal types of signals, the 18 digital lines to the VGA port are also located in the first section of the IO1 bus. The four signals of the PS2 interfaces are transmitted on lines on the higher connector section.
  
-^ Signal Name ^ Pin   (IO1-Bus) ^ [[standard:system_bus|System Bus]] Pin Name ^+^ Signal Name ^ Pin   (IO1-Bus) ^ [[gecko3:system_bus:start|System Bus]] Pin Name ^
 | **Soft JTAG Chain** ||| | **Soft JTAG Chain** |||
 | SOFT_JTAG_TCK |  7| EXTCLK0 | | SOFT_JTAG_TCK |  7| EXTCLK0 |
Line 80: Line 80:
 ===== Documents ===== ===== Documents =====
 Schematic:{{:gecko-platforms:gecko3_staddle:gecko3_staddle_schem.pdf|}}\\ Schematic:{{:gecko-platforms:gecko3_staddle:gecko3_staddle_schem.pdf|}}\\
-PCB design:{{:gecko:gecko-platforms:gecko3_staddle:gecko3_staddle_pcb.pdf|}}+PCB design:{{:gecko-platforms:gecko3_staddle:gecko3_staddle_pcb.pdf|}}
  • gecko-platforms/gecko3_staddle.1489152618.txt.gz
  • Last modified: 2021/12/20 10:49
  • (external edit)