gecko-platforms:gecko3_staddle

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gecko-platforms:gecko3_staddle [2017/03/06 12:17] – external edit 127.0.0.1gecko-platforms:gecko3_staddle [2021/12/20 10:49] (current) – external edit 127.0.0.1
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 <box 300px right | **Project details**> <box 300px right | **Project details**>
 ^ Name: | GECKO3EDU || ^ Name: | GECKO3EDU ||
-^ Maintainer| [[huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:orphaned]]||+^ Maintainer| [[:gecko-platforms:gecko3_staddle:orphaned]]||
 ^ Revision: | unknown || ^ Revision: | unknown ||
 ^ Development status: | stable || ^ Development status: | stable ||
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 ====== GECKO3 staddle ====== ====== GECKO3 staddle ======
  
-[[http://www.tu-ilmenau.de|{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:tui_logo_schwarzgruen_rgb_03.png?150| Contributed by the Ilmenau University of Technology, Ilmenau, Germany}}]]+[[http://www.tu-ilmenau.de|{{:gecko-platforms:gecko3_staddle:tui_logo_schwarzgruen_rgb_03.png?150| Contributed by the Ilmenau University of Technology, Ilmenau, Germany}}]]
  
-This platform is designed to operate a stack of several [[huce:microlab:adm:huce:microlab:huce:microlab:microlab:adm:huce:microlab:admin:projects:internal:gecko:gecko3:start]] modules and to give them computer-like interfaces.+This platform is designed to operate a stack of several [[:gecko3:start]] modules and to give them computer-like interfaces.
  
 ==== Features ==== ==== Features ====
  
-{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:staddlefront.jpg?39 |front panel}}{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:gecko3_staddle_card.jpg?400 |GECKO3 staddle}}+{{:gecko-platforms:gecko3_staddle:staddlefront.jpg?39 |front panel}}{{:gecko-platforms:gecko3_staddle:gecko3_staddle_card.jpg?400 |GECKO3 staddle}}
  
   * Euro card 3U form factor with frontpanel to assemble in modular chassis like PXI   * Euro card 3U form factor with frontpanel to assemble in modular chassis like PXI
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 ===== JTAG ===== ===== JTAG =====
-{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:staddlejtag.jpg |JTAG distribution}} +{{:gecko-platforms:gecko3_staddle:staddlejtag.jpg |JTAG distribution}} 
-{{ .:jtag-cable.png?220|JTAG cable}}+{{ :gecko-platforms:gecko3_staddle:jtag-cable.png?220|JTAG cable}}
 The platform makes it possible to configure and debug the GECKO3main modules with Xilinx tools and with Altium Designer. For this reason, a 14-pin (''Xilinx'') and a 10-pin (''Altium'') JTAG adapter port is installed on the board. While the GECKO3main module is already equipped to use the Xilinx JTAG interface, the additional Soft-JTAG feature of Altium Designer requires four additional signals. The 6-pole connector of the JTAG GECKO3main modules is used for the Hard-JTAG chain (identical to Xilinx), and the Soft-TDI and Soft-TDO are sent on the pins, which are originally designed for the RS-232 connection. The two broadcast signals, Soft-TMS and Soft-TCK, are distributed to the modules through the system bus. The platform makes it possible to configure and debug the GECKO3main modules with Xilinx tools and with Altium Designer. For this reason, a 14-pin (''Xilinx'') and a 10-pin (''Altium'') JTAG adapter port is installed on the board. While the GECKO3main module is already equipped to use the Xilinx JTAG interface, the additional Soft-JTAG feature of Altium Designer requires four additional signals. The 6-pole connector of the JTAG GECKO3main modules is used for the Hard-JTAG chain (identical to Xilinx), and the Soft-TDI and Soft-TDO are sent on the pins, which are originally designed for the RS-232 connection. The two broadcast signals, Soft-TMS and Soft-TCK, are distributed to the modules through the system bus.
  
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 For designs with Altium soft-JTAG devices the use of this adapted constraint file is required (it includes the mappings of the soft-JTAG signals to both the original RS232-header, and to GPIO-bus pins for distribution throughout the stack). For designs with Altium soft-JTAG devices the use of this adapted constraint file is required (it includes the mappings of the soft-JTAG signals to both the original RS232-header, and to GPIO-bus pins for distribution throughout the stack).
- +FIXME 
-{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:gecko3_nexus.zip|gecko3_nexus.zip}}+{{gecko-platforms:gecko3_staddle:gecko3_nexus.zip|gecko3_nexus.zip}}
  
 ===== PS/2 ===== ===== PS/2 =====
-{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:staddleps2.jpg?194 |PS/2 ports}}{{ .:bustreiber.png?200|PS/2 port schematic}}+{{:gecko-platforms:gecko3_staddle:staddleps2.jpg?194 |PS/2 ports}}{{ :gecko-platforms:gecko3_staddle:bustreiber.png?200|PS/2 port schematic}}
 There are two PS/2 ports applied to the front panel for user input via keyboard and mouse. The signals are passed through the system bus to the GECKO3main modules. Since both, the input device and the FPGA can drive the line, a short circuit by different signal levels must be prevented. This can be realized using the tri-state outputs of the FPGA, but has to be taken care of by the PS/2 component within the FPGA design. A "zero" is given active to the output, but instead of an active "one", the output is set high impedance (disable). The high level of the line is achieved by the external pull-up resistor to 5 V. There are two PS/2 ports applied to the front panel for user input via keyboard and mouse. The signals are passed through the system bus to the GECKO3main modules. Since both, the input device and the FPGA can drive the line, a short circuit by different signal levels must be prevented. This can be realized using the tri-state outputs of the FPGA, but has to be taken care of by the PS/2 component within the FPGA design. A "zero" is given active to the output, but instead of an active "one", the output is set high impedance (disable). The high level of the line is achieved by the external pull-up resistor to 5 V.
  
 ===== VGA =====  ===== VGA ===== 
-{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:staddlevga.jpg?374 |VGA DA converter}}+{{:gecko-platforms:gecko3_staddle:staddlevga.jpg?374 |VGA DA converter}}
  
 On the front panel of the card is also a VGA connector for the monitor output. The maximum depth is 16 bit (65,536 colors). In this "High Color" Graphics mode red and blue, each are coded with 5 bits and green stand for even 6 bits. If you use a display controller with less color resolution, you have to  allocate the color signals from the most to the least significant bit. The remaining lines of the platform should assigned each to the least significant color bit of the controller IP core. On the front panel of the card is also a VGA connector for the monitor output. The maximum depth is 16 bit (65,536 colors). In this "High Color" Graphics mode red and blue, each are coded with 5 bits and green stand for even 6 bits. If you use a display controller with less color resolution, you have to  allocate the color signals from the most to the least significant bit. The remaining lines of the platform should assigned each to the least significant color bit of the controller IP core.
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 ===== Power Source ===== ===== Power Source =====
-{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:staddlevcc.jpg?483 |power source}}+{{:gecko-platforms:gecko3_staddle:staddlevcc.jpg?483 |power source}}
 For power supply a DC/DC converter TEN 40-1220 by Traco Electronic is mounted on the platform. From an input voltage of 9-18 V it produces two output voltages of 3.3 V and 5 V. With the maximum output power of 40 W up to 5 GECKO3main modules can be operated. A external 12 volt power supply can be connected via a "Power Jack Connector 2.1 mm" at the front panel. Using four jumpers select between external power or PXI. For the PXI option the power is provided via the CompactPCI connector. The two voltages are each loaded with a maximum of 2 A (protected), so that on a staddle only one GECKO3main module can be operated inside a slot of a PXI rack. For power supply a DC/DC converter TEN 40-1220 by Traco Electronic is mounted on the platform. From an input voltage of 9-18 V it produces two output voltages of 3.3 V and 5 V. With the maximum output power of 40 W up to 5 GECKO3main modules can be operated. A external 12 volt power supply can be connected via a "Power Jack Connector 2.1 mm" at the front panel. Using four jumpers select between external power or PXI. For the PXI option the power is provided via the CompactPCI connector. The two voltages are each loaded with a maximum of 2 A (protected), so that on a staddle only one GECKO3main module can be operated inside a slot of a PXI rack.
  
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 Due to the use of continuous areas for equal types of signals, the 18 digital lines to the VGA port are also located in the first section of the IO1 bus. The four signals of the PS2 interfaces are transmitted on lines on the higher connector section. Due to the use of continuous areas for equal types of signals, the 18 digital lines to the VGA port are also located in the first section of the IO1 bus. The four signals of the PS2 interfaces are transmitted on lines on the higher connector section.
  
-^ Signal Name ^ Pin   (IO1-Bus) ^ [[standard:system_bus|System Bus]] Pin Name ^+^ Signal Name ^ Pin   (IO1-Bus) ^ [[gecko3:system_bus:start|System Bus]] Pin Name ^
 | **Soft JTAG Chain** ||| | **Soft JTAG Chain** |||
 | SOFT_JTAG_TCK |  7| EXTCLK0 | | SOFT_JTAG_TCK |  7| EXTCLK0 |
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 | PS2K_DATA, PS2K_CLK |  86, 88 | GPIO1_23, GPIO1_21 |  | PS2K_DATA, PS2K_CLK |  86, 88 | GPIO1_23, GPIO1_21 | 
  
-{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:system-bus.png|System Bus}}+{{:gecko-platforms:gecko3_staddle:system-bus.png|System Bus}}
  
  
 ===== Documents ===== ===== Documents =====
-Schematic:{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:gecko3_staddle_schem.pdf|}}\\ +Schematic:{{:gecko-platforms:gecko3_staddle:gecko3_staddle_schem.pdf|}}\\ 
-PCB design:{{huce:microlab:projects:internal:gecko:gecko-platform:gecko3_staddle:gecko3_staddle_pcb.pdf|}}+PCB design:{{:gecko-platforms:gecko3_staddle:gecko3_staddle_pcb.pdf|}}
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  • Last modified: 2021/12/20 10:49
  • (external edit)