gecko-addons:gecko-visual:hardware

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gecko-addons:gecko-visual:hardware [2017/03/10 08:07] – external edit 127.0.0.1gecko-addons:gecko-visual:hardware [2021/12/20 10:49] (current) – external edit 127.0.0.1
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 In this section all hardware components are introduced. The block diagram gives an overview of the interconnection of components. Main part is the Spartan 3an FPGA which serves as central unit. In this section all hardware components are introduced. The block diagram gives an overview of the interconnection of components. Main part is the Spartan 3an FPGA which serves as central unit.
  
-{{ gecko3:gecko-addon:gecko-visual:wiki_blockdiagram.png?nolink&300 | }}+{{gecko-addons:gecko-visual:wiki_blockdiagram.png?nolink&300 | }}
  
 Find more information about the functional interaction of the components in the section [[ip-architecture|]]. Find more information about the functional interaction of the components in the section [[ip-architecture|]].
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 The display is a 480x320 Pixel transmissive LCD which fulfills the size requirements of the GECKO system standard. For backlighting an external backlight driver is needed (TPS61160A). Two interfaces are provided: SPI for configuration and parallel RGB for Display data. The display is a 480x320 Pixel transmissive LCD which fulfills the size requirements of the GECKO system standard. For backlighting an external backlight driver is needed (TPS61160A). Two interfaces are provided: SPI for configuration and parallel RGB for Display data.
  
-{{gecko3:gecko-addon:gecko-visual:wiki_lcd.jpg?nolink&110 |}}+{{gecko-addons:gecko-visual:wiki_lcd.jpg?nolink&110 |}}
   * Module Name: SDT033TFT [[http://www.displaytech.com.hk/upload/product/attachment/5445-dt033tft-v21.pdf|Datasheet]]   * Module Name: SDT033TFT [[http://www.displaytech.com.hk/upload/product/attachment/5445-dt033tft-v21.pdf|Datasheet]]
   * Driver IC: D51E5TA7601 [[http://www.displaytech.com.hk/pdf/TFTModules/D51E5TA7601_V0.6.pdf|Datasheet]]   * Driver IC: D51E5TA7601 [[http://www.displaytech.com.hk/pdf/TFTModules/D51E5TA7601_V0.6.pdf|Datasheet]]
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 The camera module houses a 5 MP CMOS image sensor from omnivision. The image data is provided by a 10 bit RGB Raw Data interface. The color filters are in [[http://en.wikipedia.org/wiki/Bayer_filter|Bayer Pattern]]. An IIC interface is used for configuration purposes. The camera module houses a 5 MP CMOS image sensor from omnivision. The image data is provided by a 10 bit RGB Raw Data interface. The color filters are in [[http://en.wikipedia.org/wiki/Bayer_filter|Bayer Pattern]]. An IIC interface is used for configuration purposes.
  
-{{:gecko3:gecko-addon:gecko-visual:wiki_aa5620.jpg?130 |}}+{{gecko-addons:gecko-visual:wiki_aa5620.jpg?130 |}}
   * Module: COMedia OV5620 [[http://electronics123.net/amazon/datasheet/AA5620.pdf|Datasheet]]   * Module: COMedia OV5620 [[http://electronics123.net/amazon/datasheet/AA5620.pdf|Datasheet]]
   * Image Sensor: Omnivision OV5620 [[http://electronics123.net/amazon/datasheet/OV5620_CLCC_DS%20%281.3%29.pdf|Datasheet]]   * Image Sensor: Omnivision OV5620 [[http://electronics123.net/amazon/datasheet/OV5620_CLCC_DS%20%281.3%29.pdf|Datasheet]]
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 === Schematic ===   === Schematic ===  
  
-{{:gecko3:gecko-addon:gecko-visual:gecko_visual_schem.pdf|}}+{{:gecko-addons:gecko-visual:gecko_visual_schem.pdf|}}
  
 === Powering === === Powering ===
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 === PCB Layout === === PCB Layout ===
  
-{{gecko3:gecko-addon:gecko-visual:gecko_visual_pcb.pdf|}}+{{:gecko-addons:gecko-visual:gecko_visual_pcb.pdf|}}
  
 The image shows the PCB Stackup. The PCB consists of 4 signal layers and 2 power planes (located in the middle). The image shows the PCB Stackup. The PCB consists of 4 signal layers and 2 power planes (located in the middle).
-{{ :huce:microlab:projects:internal:gecko:gecko-addon:gecko-visual:wiki_stack.jpg?nolink&450 |}}+{{ :gecko-addons:gecko-visual:wiki_stack.jpg?nolink&450 |}}
  
 Layout FPGA Layout FPGA
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 The FPGA comes in a FT256 BGA with 1mm pitch. To route the I/O's vias are placed between each pin: The FPGA comes in a FT256 BGA with 1mm pitch. To route the I/O's vias are placed between each pin:
  
-{{gecko3:gecko-addon:gecko-visual:wiki_fpga_layout.jpg?nolink&150|}}+{{gecko-addons:gecko-visual:wiki_fpga_layout.jpg?nolink&150|}}
  
 Layout SDRAM Layout SDRAM
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 Due to the high speed of SDRAM signals all lines to the memory are length matched: Due to the high speed of SDRAM signals all lines to the memory are length matched:
  
-{{:gecko3:gecko-addon:gecko-visual:wiki_ram_layout.jpg?nolink&150|}}+{{:gecko-addons:gecko-visual:wiki_ram_layout.jpg?nolink&150|}}
  
  
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  • Last modified: 2021/12/20 10:49
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