User clocks

The GPIO1 connector on the GECKO4main provides two user clocks. These clocks are connected to the GECKO4com for level adaptation. In the GECKO4com these two clocks are put on a Digital Loop Lock (DLL) for timing compensation. The GECKO4com provides the user clocks including a lock signal to the user FPGA. If the lock signal is 0 the clocks should not be used, and if the lock signal is 1 the clock is stable and locked by the GECKO4com. The DLL used in the GECKO4com poses some restriction on the user clocks. The restriction is the frequency range a user clock is allowed to have. The user clocks must be in the range of [18MHz…167MHz] with a duty cycle in between 40% and 60%.