====== Project Description ======
==== FPGA ====
Xilinx Spartan3 FG 676, size varies between 1.5 and 4 million System gates. -> [[http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf|Datasheet]]

The modules used at the [[http://www.microlab.ch/|MicroLab]] contain a Spartan3 XC3S4000-FGG676 FPGA.

^  Device  ^  System Gates  ^  Equivalent Logic Cells  ^  Total CLBs  ^  Distributed RAM Bits  ^  Block RAM Bits  ^  Dedicated Multipliers  ^  Digital Clock Managers  ^
| XC3S1500 |  1.5M |  29,952 |  3,328 |  208K |   576K |  32 |  4 |
| XC3S2000 |  2M |  46,080 |  5,120 |  320K |   720K |  40 |  4 |
| XC3S4000 |  4M |  62,208 |  6,912 |  432K |  1,728K |  96 |  4 |


==== Clock sources ====
  * On board oscillator with a frequency of 50 MHz 
  * Two external clock inputs (''EXTCLK0'' and ''EXTCLK1'') as described on the [[gecko3:system_bus:start|system bus]] page